1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device and data processing methods thereof which can perform a write operation after 1 or 2 cycles and additionally bypass an input data when write and read addresses are same while a read operation is performed after the write operation.
2. Description of the Prior Art
A conventional semiconductor memory device is designed to perform a write operation through the following processes after 1 or 2 cycles. That is, a write address input from the outside the device is first input into an address decoder while the periods of 1 or 2 cycles are delayed in the device, and then word and bit lines are selected. After the write address input, external data signals are transmitted to a write driver after a 1 or 2 cycle delay, and then the write operation is performed after this delay.
Performing the write operation after 1 or 2 cycles means that when the write address is input, the semiconductor memory device receives the write data input from the outside after the delay of 1 or 2 cycles from the input of the write address, before performing the writing operation.
The conventional semiconductor memory device can perform the writing function after 1 or 2 cycles, but cannot perform a bypassing function. That is, in a case that a write command is input 2 cycles prior to a read command, or a write is input 1 or 2 cycles prior to a read command, the conventional semiconductor memory device performs a limited bypass function by which a write data is output toward the outside thereof through a buffer without being stored in a memory cell.
However, in the conventional semiconductor device a bypass function could not be performed if a read command was input just after a write command was input, and when a write address and a read address were the same.